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HT82M9BEE/HT82M9BAE USB Mouse Encoder 8-Bit MCU with EEPROM
Technical Document
* Tools Information * FAQs * Application Note
Features
* Flexible total solution for applications that combine * 6MHz/12MHz internal CPU clock * 8-level stacks * Two 8-bit indirect addressing registers * One 8-bit programmable timer counter with overflow
PS/2 and low-speed USB interface, such as mice, joysticks, and many others
* USB Specification Compliance - Conforms to USB specification V1.1 - Conforms to USB HID specification V1.1 * Supports 1 low-speed USB control endpoint and
interrupt (shared with PA6, vector 08H)
* One 16-bit programmable timer counter with
3 interrupt endpoint
* Each endpoint has 88 bytes FIFO * Integrated USB transceiver * 3.3V regulator output * External 6MHz or 12MHz ceramic resonator or crystal * 8-bit RISC microcontroller, with 8K16 program
overflow interrupt (shared with PA7, vector 0CH)
* One USB interrupt input (vector 04H) * HALT function and wake-up feature reduce power
consumption
* PA0~PA7, PB4/SDA and PB7/SCL support wake-up
function
* Internal Power-On reset (POR) * Watchdog Timer (WDT) * 20 I/O ports * 24/28-pin SOP package
memory (0000H~1FFFH)
* 2248 bytes RAM (20H~FFH) * EEPROM 1288 data memory
General Description
The USB MCU OTP body is suitable for USB mouse and USB joystick devices. It consists of a Holtek high performance 8-bit MCU core for control unit, built-in USB SIE, 8K16 ROM and 224 bytes data RAM. The mask version HT82M9BAE is fully pin and functionally compatible with the OTP version HT82M9BEE device. There are two dice in the HT82M9BEE/HT82M9BAE package: one is the HT82M9BE/HT82M9BA MCU, the other is a 1288 bits EEPROM used for data memory purpose. The two dice are wrie-bonded to from HT82M9BEE/ HT82M9BAE.
Rev. 1.20
1
August 13, 2007
HT82M9BEE/HT82M9BAE
Block Diagram
U S B D + /C L K U S B D -/D A T A V33O TM R1C M U X U S B 1 .1 PS2 BP In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C TM R0 TM R0C M U X fS
YS
fS
YS
/4 P A 7 /T M R 1
TM R1
/4
P A 6 /T M R 0
E N /D IS W DTS In s tr u c tio n R e g is te r W D T P r e s c a le r MP M U X D a ta M e m o ry PAC PA In s tr u c tio n D ecoder ALU S h ifte r MUX PBC PB P o rt B WDT PA6 PA7 P o rt A PA0~PA5 P A 6 /T M R 0 P A 7 /T M R 1 M U X S Y S C L K /4 W DT OSC
T im in g G e n e ra to r
STATUS
PB PB PB PB
0~P 4 /S 5~P 7 /S
B3 DA B6 CL
OSC2
OS R V V
C1 ES DD SS
PCC ACC PC
P o rt C
PC 0~PC3
Pin Assignment
PC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PC3 PB5 1 2 3 4 5 6 7 8 9 10 11 12 PB6 VSS V33O U S B D + /C L K U S B D -/D A T A RES PA0 PA1 PB2 PB3 P B 4 /S D A 24 23 22 21 20 19 18 17 16 15 14 13 2 4 S O P -A PB1 PB0 OSCI OSCO VDD PA7 PA6 PA5 PA4 PA3 PA2 P B 7 /S C L PB5 PB6 VSS V33O U S B D + /C L K U S B D -/D A T A RES PA0 PA1 PB2 PB3 P B 4 /S D A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 2 8 S O P -A PC1 PC0 PB1 PB0 OSCI OSCO VDD PA7 PA6 PA5 PA4 PA3 PA2 P B 7 /S C L
H T 8 2 M 9 B E E /H T 8 2 M 9 B A E
H T 8 2 M 9 B E E /H T 8 2 M 9 B A E
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Pin Description
Pin Name I/O ROM Code Option Description
PA0~PA7
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is controlled by PAC (PA control register). Pull-high Pull-high resistor options: PA0~PA7 Pull-low I/O Pull-low resistor options: PA0~PA3 Wake-up CMOS/NMOS/PMOS CMOS/NMOS/PMOS options: PA0~PA7 Falling edge wake-up options: PA0~PA1, PA4~PA7 Rising and falling edge wake-up options: PA2~PA3 Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). PB4 is wire-bonded with the SDA pad of the Data EEPROM. PB7 is wire-bonded with the SCL pad of the Data EEPROM. Pull-high resistor options: PB0~PB7 Pull-low resistor for options: PB2, PB3 Falling edge wake-up options: PB4/SDA, PB7/SCL Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). Pull-high resistor options: PC0~PC3 Negative power supply, ground Schmitt trigger reset input. Active low. Positive power supply 3.3V regulator output USBD+ or PS2 CLK I/O line USB or PS2 function is controlled by software control register USBD- or PS2 DATA I/O line USB or PS2 function is controlled by software control register OSCI, OSCO are connected to a 6MHz or 12MHz crystal/resonator (determined by software instructions) for the internal system clock.
PB0~PB3 PB4/SDA PB5~PB6 PB7/SCL
I/O
Pull-high Pull-low Wake-up
PC0~PC3
I/O
Pull-high
VSS RES VDD V33O USBD+/CLK USBD-/DATA OSCI OSCO
3/4 I 3/4 O I/O I/O I O
3/4 3/4 3/4 3/4 3/4 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Storage Temperature ............................-50C to 125C Operating Temperature...............................0C to 70C IOH Total............................................................-100mA
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HT82M9BEE/HT82M9BAE
D.C. Characteristics
Symbol VDD IDD1 IDD2 ISTB1 ISTB2 ISTB3 ISTB4 VIL1 VIH1 VIL2 VIH2 IOL IOH RPD RPH1 RPH2 RPH3 VLVR Parameter Operating Voltage Operating Current (6MHz Crystal) Operating Current (12MHz Crystal) Standby Current (WDT Enable) Standby Current (WDT Disable) Standby Current (WDT Enable) Standby Current (WDT Disable) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) Output Sink Current for I/O Ports Output Port Source Current Pull-down Resistance for PA0~PA3, PB2 and PB3 Pull-high Resistance for DATA(*) Pull-high Resistance for CLK Pull-high Resistance for I/O Ports Low Voltage Reset Test Conditions VDD 3/4 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 3/4 3/4 3/4 5V VOL=0.4V VOL=3.4V 3/4 3/4 3/4 3/4 3/4 Conditions 3/4 No load, fSYS=6MHz No load, fSYS=12MHz No load, system HALT, USB suspend No load, system HALT, input/output mode, set SUSPEND2 [1CH].4 3/4 3/4 3/4 3/4 Min. 3.3 3/4 3/4 3/4 3/4 3/4 3/4 0 2.0 0 0.8VDD 2 -2.5 10 1.3 2.0 30 2.0 Typ. 3/4 7 8 3/4 3/4 3/4 3/4 1.2 3/4 3/4 3/4 4 -4 30 1.5 4.7 50 2.4 Max. 5.5 9 16 250 230 30 15 1.4 5.0 0.5VDD VDD 3/4 3/4 50 2.0 6.0 70 3 Ta=25C Unit V mA mA mA mA mA mA V V V V mA mA kW kW kW kW V
Note: * The DATA pull-high must be implemented by the external 1.5kW
A.C. Characteristics
Symbol fSYS fRCSYS tWDT tRF tSST tOSC Parameter System Clock (Crystal OSC) RC Clock with 8-bit Prescaler Register Watchdog Time-out Period (System Clock) USBD+, USBD- Rising & falling Time System Start-up Timer Period Crystal Setup Test Conditions VDD 5V 5V 3/4 3/4 3/4 3/4 Conditions 3/4 3/4 Without WDT prescaler 3/4 Wake-up from HALT 3/4 Min. 6 0 1024 75 3/4 3/4 Typ. 3/4 32 3/4 3/4 1024 5 Max. 12 3/4 3/4 300 3/4 10
Ta=25C Unit MHz kHz tRCSYS ns tSYS ms
Note: Power-on period=tWDT+tSST+tOSC WDT Time-out in normal mode=1/fRCSYS256WDTS+tWDT WDT Time-out in HALT mode=1/fRCSYS256WDTS+tSST+tOSC
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EEPROM A.C. Characteristics Symbol fSK tHIGH tLOW tr tf tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tAA tBUF Parameter Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time START Condition Setup Time Data Input Hold Time Data Input Setup Time STOP Condition Setup Time Output Valid from Clock Bus Free Time Input Filter Time Constant (SDA and SCL Pins) Write Cycle Time Note Note After this period the first clock pulse is generated Only relevant for repeated START condition 3/4 3/4 3/4 3/4 Time in which the bus must be free before a new transmission can start Noise suppression time 3/4 Remark 3/4 3/4 3/4 Standard Mode* Min. 3/4 4000 4700 3/4 3/4 4000 4000 0 200 4000 3/4 4700 Max. 100 3/4 3/4 1000 300 3/4 3/4 3/4 3/4 3/4 3500 3/4 VCC=5V10% Min. 3/4 600 1200 3/4 3/4 600 600 0 100 600 3/4 1200 Max. 400 3/4 3/4 300 300 3/4 3/4 3/4 3/4 3/4 900 3/4 kHz ns ns ns ns ns ns ns ns ns ns ns Ta=25C Unit
tSP tWR
3/4 3/4
100 5
3/4 3/4
50 5
ns ms
Note: These parameters are periodically sampled but not 100% tested * The standard mode means VCC=2.2V to 5.5V For relative timing, refer to timing diagrams
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Functional Description
Execution Flow The system clock for the microcontroller is derived from either 6MHz or 12MHz crystal oscillator, which used a frequency that is determined by the SCLKSEL bit of the SCC Register. The default system frequency is 12MHz. The system clock is internally divided into four nonoverlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory.
T1 T2 T3 T4 T1 T2
After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading to the PCL register, performing a subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the current program ROM page. When a control transfer takes place, an additional dummy cycle is required.
T3 T4 T1 T2 T3 T4
S y s te m
C lo c k
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow
Mode Initial Reset USB Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter *12 0 0 0 0 *11 0 0 0 0 *10 0 0 0 0 *9 0 0 0 0 *8 0 0 0 0 *7 0 0 0 0 *6 0 0 0 0 *5 0 0 0 0 *4 0 0 0 0 *3 0 0 1 1 *2 0 1 0 1 *1 0 0 0 0 *0 0 0 0 0
Program Counter+2 *12 #12 S12 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *12~*0: Program counter bits #12~#0: Instruction code bits S12~S0: Stack register bits @7~@0: PCL bits
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Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 819216 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H * Table location
Any location in the program memory can be used as look-up tables. There are three method to read the ROM data by two table read instructions: TABRDC and TABRDL, transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). The three methods are shown as follows:
This area is reserved for program initialization. After a chip reset, the program always begins execution at location 000H.
* Location 004H
The instructions TABRDC [m] (the current page, one page=256words), where the table locations is defined by TBLP (07H) in the current page. And the ROM code option TBHP is disabled (default). The instructions TABRDC [m], where the table locations is defined by registers TBLP (07H) and TBHP (01FH). And the ROM code option TBHP is enabled. The instructions TABRDL [m], where the table locations is defined by Registers TBLP (07H) in the last page (1F00H~1FFFH).
This area is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Location 00CH
This location is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
000H 004H 008H 00CH D e v ic e In itia liz a tio n P r o g r a m U S B In te r r u p t S u b r o u tin e T im In T im In e te e te r/E rru r/E rru ve pt ve pt nt Su nt Su Co br Co br un ou un ou te tin te tin r0 e r1 e
P ro g ra m M e m o ry
n00H nFFH
L o o k - u p T a b le ( 2 5 6 w o r d s )
1FFFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 6 - B its N o te : n ra n g e s fro m 0 to 1 F
Program Memory
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H, 1FH), which indicates the table location. Before accessing the table, the location must be placed in the TBLP and TBHP (If the OTP option TBHP is disabled, the value in TBHP has no effect). The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements. Once TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value. Otherwise, the ROM code option TBHP is disabled, the instruction TABRDC [m] reads the ROM Table Location
Instruction TABRDC [m] TABRDL [m]
*12 P12 1
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *12~*0: Table location bits @7~@0: TBLP bits P12~P8: Current program counter bits when TBHP is disabled TBHP register bit4~bit0 when TBHP is enabled
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data as defined by TBLP and the current program counter bits. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 4 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 4 return addresses are stored). Data Memory - RAM for Bank 0 The data memory is designed with 2248 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (2248). Most are read/write, but some are read only. The unused spaces before the 20H is reserved for future expanded usage and reading these locations will get 00H. The general purpose data memory, addressed from 20H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0 or MP1). Data Memory - RAM for Bank 1 The special function registers used in the USB interface are located in RAM Bank1. In order to access Bank1 register, only the Indirect addressing pointer MP1 can be used and the Bank register BP should be set to 1. The RAM bank 1 mapping is as shown. Address 00~1FH in RAM Bank0 and Bank1 are located in the same Registers
Bank 0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H TBHP G e n e ra l P u rp o s e D a ta M e m o ry (2 2 4 B y te s ) FFH USC USR SCC TM R0 TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C
Bank 0 RAM Mapping Indirect Addressing Register Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1). Reading location 00H (02H) indirectly will return the result 00H. Writing indirectly results in no operation. The indirect addressing pointer (MP0) always points to Bank0 RAM addresses no matter the value of Bank Register (BP). The indirect addressing pointer (MP1) can access Bank0 or Bank1 RAM data according to the value of BP which is set to 0 or 1 respectively. The memory pointer registers (MP0 and MP1) are 8-bit registers.
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Bank 1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH TBHP P ip e _ c tr l AW R STALL S IE S M IS C E n d p t_ E N F IF O 0 F IF O 1 F IF O 2 F IF O 3 USC USR SCC TM R0 TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by
Bank 1 RAM Mapping Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: Rev. 1.20 9
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HT82M9BEE/HT82M9BAE
Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register a branch to a subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. The USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC) will be set.
* Access of the corresponding USB FIFO from PC * The USB suspend signal from PC * The USB resume signal from PC * USB Reset signal
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
the interrupt has been served, the corresponding bit should be cleared by firmware. When the HT82M9BEE/HT82M9BAE receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT82M9BEE/HT82M9BAE is set and a USB interrupt is also triggered. When the HT82M9BEE/HT82M9BAE receives a Resume signal from the Host PC, the resume line (bit3 of the USC) of the HT82M9BEE/HT82M9BAE are set and a USB interrupt is triggered. Whenever a USB reset signal is detected, the USB interrupt is triggered and URST_Flag bit of the USC register is set. When the interrupt has been served, the bit should be cleared by firmware. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (bit 5 of the INTC), caused by a Timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. Function
When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host access the FIFO of the HT82M9BEE/HT82M9BAE, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So user can easily decide which FIFO is accessed. When Bit No. 0 1 2 3 4 5 6 7 Label EMI EUI ET0I ET1I USBF T0F T1F 3/4
Controls the master (global) interrupt (1=enable; 0=disable) Controls the USB interrupt (1=enable; 0= disable) Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable) USB interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1:active; 0:inactive) Internal Timer/Event Counter 1 request flag (1:active; 0:inactive) Unused bit, read as 0 INTC (0BH) Register
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The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (bit 6 of the INTC0), caused by a Timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source USB interrupt Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Priority Vector 1 2 3 04H 08H 0CH Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator), or instruction clock (system clock divided by 4), determine by ROM code option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by ROM code option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with a period of 31ms/5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 8ms/5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 1s/5V. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external
W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
This oscillator is designed for system clocks. The HALT mode stops the system oscillator and ignores an external signal to conserve power. A crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The HT82M9BEE/HT82M9BAE can operate in 6MHz or 12MHz system clocks. In order to make sure that the USB SIE functions properly, user should correctly configure the SCLKSEL bit of the SCC Register. The default system clock is 12MHz. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works within a period of approximately 31ms. The WDT oscillator can be disabled by ROM code option to conserve power.
Once the interrupt request flags (T0F/T1F, USBF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There is an oscillator circuit in the microcontroller.
OSC1
OSC2 C r y s ta l O s c illa to r
System Oscillator
S y s te m C lo c k /4
W DT OSC
ROM Code O p tio n S e le c t
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
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logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, which can only be set to 10000 (WDTS.7~WDTS.3). If the device operates in a noisy environment, using the on-chip 32kHz RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the cause for chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; the others remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are four ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation * USB reset
WDTS (09H) Register The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. But in the HALT mode, the overflow will initialize a warm reset and only the program counter and SP are reset to zero. To clear the contents of the WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a HALT instruction. The software instruction include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the ROM code option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times is equal to one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT and CLR WDT are chosen (i.e. CLRWDT times is equal to two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following:
* The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected). * The contents of the on-chip RAM and registers remain unchanged.
* The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator). * All of the I/O ports remain in their original status.
* The PDF flag is set and the TO flag is cleared.
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the program counterand SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets.
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TO PDF 0 u 0 1 1 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT Reset Circuit
VDD RES S S T T im e - o u t C h ip R eset tS
ST
V
DD
RES
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler WDT 000H Disable Clear Clear. After master reset, WDT begins counting
RES
Reset Timing Chart
HALT W DT
W a rm
R eset
OSC1
Timer/event Counter Off Input/output Ports Stack Pointer Input mode Points to the top of the stack
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Configuration
The registers status are summarized in the following table. Reset (Power On) WDT Time-out (Normal Operation) 000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 1000 0111 --1u uuuu -000 0000 0000 0000 RES Reset (Normal Operation) 000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 1000 0111 --00 uuuu -000 0000 0000 0000 RES Reset (HALT) WDT Time-out (HALT)* 000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu USB Reset (Normal) USB Reset (HALT)
Register
Program Counter MP0 MP1 BP ACC TBLP TBLH WDTS STATUS INTC TMR0
000H xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx 1000 0111 --00 xxxx -000 0000 xxxx xxxx
000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 1000 0111 --00 uuuu -000 0000 0000 0000
000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 1000 0111 --uu uuuu -000 0000 uuuu uuuu
000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 1000 0111 --01 uuuu -000 0000 uuuu uuuu
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Reset (Power On) 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 11xx 0000 0000 0000 0000 0000 0000 0000 0000 1110 0000 0000 0000 1110 0100 0000 0x00 0000 0000 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx WDT Time-out (Normal Operation) 00-0 1--0000 0000 0000 0000 00-0 1--xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 xxxx 1111 xxxx 11xx xuux u0uu 0u00 uu00 u000 000u uuuu 0000 0uuu uuuu uuuu 0000 uuuu uuuu uuuu uuuu uuuu 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu RES Reset (Normal Operation) 00-0 1--0000 0000 0000 0000 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 11xx 0000 0000 0000 0000 0000 000u uuuu 0000 1110 0000 0000 0000 1110 0100 0000 0000 0000 0000 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu RES Reset (HALT) 00-0 1--0000 0000 0000 0000 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 11xx 0000 0000 0000 0000 0000 000u uuuu 0000 1110 0000 0000 0000 1110 0100 0000 0000 0000 0000 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu WDT Time-out (HALT)* uu-u u--uuuu uuuu uuuu uuuu uu-u u--xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 xxxx 1111 xxxx 11xx xuux u0uu uuuu uu0u u000 000u uuuu 0000 1110 uuuu uuuu 0000 uuuu uuuu uuuu uuuu uuuu 0000 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB Reset (Normal) 00-0 1--uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1100 0u00 u1uu 0000 uu00 u000 000u uuuu 0000 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000 USB Reset (HALT) 00-0 1--uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1100 0u00 u1uu 0000 uu00 u000 000u uuuu 0000 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000
Register
TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC PC PCC USC USR SCC TBHP Pipe_ctrl AWR STALL SIES MISC Endpt_EN FIFO0 FIFO1 FIFO2 FIFO3
Note: * stands for warm reset u stands for unchanged x stands for unknown
Timer/Event Counter Two timer/event counters (TMR0, TMR1) are implemented in the microcontroller. The Timer/Event Counter 0 contains an 8-bit programmable count-up counter and the clock may comes from an external source or from fSYS/4. The Timer/Event Counter 1 contains an 16-bit programmable count-up counter and the clock may come from an external source or from the system clock divided by 4. Using the internal clock source, there is only 1 reference time-base for Timer/Event Counter 0. The internal clock source is coming from fSYS/4.
The external clock input allows the user to count external events, measure time intervals or pulse widths. Using the internal clock source, there is only 1 reference time-base for Timer/Event Counter 1. The internal clock source is coming from fSYS/4. The external clock input allows the user to count external events, measure time intervals or pulse widths. There are 2 registers related to the Timer/Event Counter 0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical registers are mapped to TMR0 location; writing TMR0 makes the starting value be placed in the Timer/Event Counter 0 preload register and reading TMR0 gets the contents of the Timer/Event Counter 0. The TMR0C is a timer/event counter control register, which defines some options.
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There are 3 registers related to Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing TMR1L will only put the written data to an internal lower-order byte buffer (8 bits) and writing TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H and TMR1L preload registers, respectively. The Timer/Event Counter 1 preload register is changed by each writing TMR1H operations. Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destination and the lower-order byte buffer, respectively. Reading the TMR1L will read the contents of the lower-order byte buffer. The TMR1C is the Timer/Event Counter 1 control register, which defines the operating mode, counting enable or disable and active edge. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR0/TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the fSYS/4 (Timer0/Timer1). The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0/TMR1). The counting is based on the fSYS/4 (Timer0/Timer1). In the event count or timer mode, once the Timer/Event Counter 0/1 starts counting, it will count from the current contents in the Timer/Event Counter 0/1 to FFH or FFFFH. Once overflow occurs, the counter is reloaded from the Timer/Event Counter 0/1 preload register and generates the interrupt request flag (T0F/T1F; bit 5/6 of INTC) at the same time. Bit No. 0~2, 5 3 4 Label 3/4 TE TON Unused bit, read as 0 To define the TMR0 active edge of Timer/Event Counter 0 (0=active on low to high; 1=active on high to low) To enable/disable timer 0 counting (0=disabled; 1=enabled) To define the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register Bit No. 0~2, 5 3 4 Label 3/4 TE TON Unused bit, read as 0 To define the TMR1 active edge of Timer/Event Counter 1 (0=active on low to high; 1=active on high to low) To enable/disable timer 1 counting (0=disabled; 1=enabled) To define the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register Function In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR0/TMR1 has received a transient from low to high (or high to low if the TE bits is 0) it will start counting until the TMR0/TMR1 returns to the original level and resets the TON. The measured result will remain in the Timer/Event Counter 0/1 even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the Timer/Event Counter 0/1 starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter 0/1 is reloaded from the Timer/Event Counter 0/1 preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt services. In the case of Timer/Event Counter 0/1 OFF condition, writing data to the Timer/Event Counter 0/1 preload register will also reload that data to the Timer/Event Counter 0/1. But if the Timer/Event Counter 0/1 is turned on, data written to it will only be kept in the Timer/Event Counter 0/1 preload register. The Timer/Event Counter 0/1 will still Function
6 7
TM0 TM1
6 7
TM0 TM1
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fS
YS
/4
D a ta B u s TM 1 TM 0 TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r 0 O v e r flo w to In te rru p t T im e r /E v e n t C o u n te r 0 P r e lo a d R e g is te r R e lo a d
TM R0
Timer/Event Counter 0
D a ta B u s fS
Y S /4
TM R1 TE TM 1 TM 0 TON
TM 1 TM 0
1 6 B its T im e r /E v e n t C o u n te r P r e lo a d R e g is te r
L o w B y te B u ffe r R e lo a d
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
1 6 B its T im e r /E v e n t C o u n te r (T M R 1 H /T M R 1 L )
O v e r flo w to In te rru p t
Timer/Event Counter 1 operate until overflow occurs (a Timer/Event Counter 0/1 reloading will occur at the same time). When the Timer/Event Counter 0/1 (reading TMR0/TMR1) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer. Input/Output Ports There are 20 bidirectional input/output lines in the microcontroller, labeled from PA to PC, which are mapped to the data memory of [12H], [14H] and [16H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC and PCC) to control the input/output configuration. With this control register, CMOS/NMOS/PMOS output or Schmitt trigger input with or without pull-high/low resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a 1. The input source
V C o n tr o l B it Q D CK S Q P u ll- h ig h
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D a ta B it Q D CK S Q P u ll- lo w M U X
P A , P B 4 , P B 7 W a k e - u p O p tio n
W r ite D a ta R e g is te r
P o rt O u tp u t C o n fig u r a tio n R e a d D a ta R e g is te r P A , P B 4 , P B 7 W a k e -u p P A 6 /T M R 0 P A 7 /T M R 1
PA PB PB PB PB PC
0~ 0~ 4 /S 5~ 7 /S 0~
PA PB D PB C PC L
A 6
3
5 , P A 6 /T M R 0 , P A 7 /T M R 1
3
Input/Output Ports
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also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS/NMOS/PMOS configurations can be selected (NMOS and PMOS are available for PA only). These control registers are mapped to locations 13H 15H and 17H. After a chip reset, these input/output lines remain at high levels or in a floating state (depending on the pull-high/low options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H or 16H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of PA0~PA7, PB4/SDA and PB7/SCL has the capability of waking-up the device.
V 2 .7 V 2 .4 V
Low Voltage Reset - LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device drops to within the range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* For a valid LVR signal, a low voltage (0.9V~VLVR) must
exist for more than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
* The LVR uses the OR function with the external
RES signal to perform a chip reset. The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
LVR
There are pull-high/low options available for I/O lines. Once the pull-high/low option of an I/O line is selected, the I/O line have pull-high/low resistor. Otherwise, the pull-high/low resistor is absent. It should be noted that a non-pull-high/low I/O line operating in input mode will cause a floating state. It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state.
0 .9 V
Note: VOPR is the voltage range for proper chip operation at 6MHz or 12MHz system clock.
V 5 .5 V
DD
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode.
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Data EEPROM Functional Description
* Serial clock (SCL)
Device Addressing The 1K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation. The device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram showing the Device Address). This is common to all the EEPROM device. The next three bits are the fixed to be 0. The 8th bit of device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state.
1 0 1 0 0 0 0 R /W
The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device.
* Serial data (SDA)
The SDA pin is bidirectional for serial data transfer. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices. Memory Organization
* 1K Serial EEPROM
Internally organized with 128 8-bit words, the 1K requires an 8-bit data word address for random word addressing. Device Operations
* Clock and data transition
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition.
* Start condition
D e v ic e A d d r e s s
Write Operations
* Byte write
A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition Timing diagram).
* Stop condition
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).
* Acknowledge
A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the non-volatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until the write is completed (refer to Byte write timing).
* Acknowledge polling
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
D a ta a llo w e d to c h a n g e SDA
To maximise bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received.
SCL S ta rt c o n d itio n A d d re s s o r a c k n o w le d g e v a lid NoACK s ta te
S to p c o n d itio n
D e v ic e a d d r e s s SDA S S ta rt R /W ACK
W o rd a d d re s s
DATA P ACK ACK S to p
Byte Write Timing
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S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n to In itia te W r ite C y c le S e n d S ta rt S e n d C o tr o ll B y te w ith R /W = 0
last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller should respond a No ACK (High) signal and following stop condition (refer to Current read timing).
* Random read
(A C K = 0 )? Yes N e x t O p e r a tio n
No
Acknowledge Polling Flow
* Read operations
A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller should respond with a no ACK signal (high) followed by a stop condition. (refer to Random read timing).
* Sequential read
The data EEPROM supports three read operations, namely, current address read, random address read and sequential read. During read operation execution, the read/write select bit should be set to 1.
* Current address read
The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll over during read from the last byte of the last memory page to the first byte of the first page. The address roll over during write from the
Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the microcontroller responds with a no ACK signal (high) followed by a stop condition.
D e v ic e a d d r e s s SDA S S ta rt ACK
DATA
S to p P NoACK
Current Read Timing
D e v ic e a d d r e s s SDA S S ta rt ACK
W o rd a d d re s s S
D e v ic e a d d r e s s
DATA
S to p P NoACK
ACK S ta rt
ACK
Random Read Timing
D e v ic e a d d r e s s SDA S
DATA n
DATA n+1
DATA n+x
S to p P NoACK
S ta rt
ACK
ACK
Sequential Read Timing
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HT82M9BEE/HT82M9BAE
Data EEPROM Timing Diagrams
tf SCL tS
U
tr tL
OW D
tH
IG H
:S
TA
tH tS
P
:S
TA
tH
D
:D
AT
tS
U
:D
AT
tS
U
:S
TO
SDA SDA OUT
tA
A
tB V a lid V a lid
UF
SCL SDA 8 th b it W o rd n S to p C o n d itio n
ACK tW
R
S ta rt C o n d itio n
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.
USB with MCU Interface
There are eight registers, including Pipe_ctrl, Address+Remote_WakeUp, STALL, SIES, MISC, Endpt_EN and FIFO0~FIFO3 in this buffer function. Register Name Mem. Addr. Pipe_ctrl 41H Addr.+ STALL Remote 42H 43H SIES 45H MISC 46H Endpt_EN FIFO0 47H 48H FIFO1 49H FIFO2 4AH FIFO3 4BH
Register Memory Mapping Address+Remote_WakeUp register represents current address and remote wake-up function. The initial value is 00000000 from MSB to LSB. Register Address 01000010B R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Remote Wake-up Function 0: Not this function 1: The function exists
R/W
Address value Default value=00000000 Address+Remote_WakeUp Register
STALL, Pipe_ctrl and Endpt_EN Registers PIPE register represents whether the endpoint corresponding is accessed by host or not. After ACT_EN signal being sent out, MCU can check which endpoint had been accessed. This register is set only after the time when host access the corresponding endpoint. STALL register shows whether the endpoint corresponding works or not. As soon as the endpoint work improperly, the bit corresponding must be set. Pipe_ctrl register is used for configuring IN (Bit=1) or OUT (Bit=0) pipe. The default is define IN pipe. Where Bit0 (DATA0) of the Pipe_ctrl register is used to setting the data toggle of any endpoint (except endpoint 0) using data toggles to the value DATA0. Once the user want the any endpoint (except endpoint 0) using data toggles to the value DATA0, the user can output a LOW pulse to this bit. The LOW pulse period must at least 10 instruction cycle. Endpt_EN register is used to enable or disable the corresponding endpoint (except endpoint 0). Enable Endpoint (Bit=1) or disable Endpoint (Bit=0). Rev. 1.20 20 August 13, 2007
HT82M9BEE/HT82M9BAE
The bitmaps are list as follows: Register Name Pipe_ctrl STALL Endpt_EN R/W R/W R/W R/W Register Address 01000001B 01000011B 01000111B Bit7~Bit4 Reserved 3/4 3/4 3/4 Bit 3 Pipe 3 Pipe 3 Pipe 3 Bit 2 Pipe 2 Pipe 2 Pipe 2 Bit 1 Pipe 1 Pipe 1 Pipe 1 Bit 0 Data 0 Pipe 0 Pipe 0 Default Value 0000 1110 0000 1110 0000 1111
Pipe_ctrl (41H), STALL (43H) and Endpt_EN (47H) Registers The SIES Register is used to indicate the present signal state which the USB SIE received and also determines whether the USB SIE has to change the device address automatically. Bit No. 7 6 5 4 3 2 1 0 Function MNI EOT CRC_ERR NAK IN OUT F0_ERR Adr_set Read/Write R/W R R/W R 01000101B R R/W R/W R/W Register Address
SIES (45H) Registers Table Function Name
Read/Write
Description This bit is used to configure the USB SIE to automatically change the device address with the value of the Address+Remote_WakeUp Register (42H). When this bit is set to 1 by F/W, the USB SIE will update the device address with the value of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully read the data from the device by the IN operation. The USB SIE will clear the bit after updating the device address. Otherwise, when this bit is cleared to 0, the USB SIE will update the device address immediately after an address is written to the Address+Remote_WakeUp Register (42H). This bit is used to indicate when there are some errors that occurred when the FIFO0 is accessed. This bit is set by the USB SIE and cleared by F/W. This bit is used to indicate that there are OUT token (except for the OUT zero) that has been received. The F/W clears the bit after the OUT data has been read. Also, this bit will be cleared by the USB SIE after the next valid SETUP token is received. This bit is used to indicate that the current USB receiving signal from the PC Host is IN token. This bit is used to indicate that the USB SIE has transmitted the NAK signal to the Host in response to the PC Host IN or OUT token. This bit indicates that there are CRC error (bit=1). The programmer must do something to save the device and keep it alive. This bit is set by the USB SIE and cleared by F/W. End of transient flag, normal status is 1. If suspend=1 line & EOT=0 indicates that something is wrong in the USB Interface. The programmer must do something to save the device and keep it alive. This bit is for masking the NAK interrupt when MNI=1, the default value=0 SIES Function Table
Adr_set
R/W
F0_Err
R/W
Out
R/W
IN NAK
R R
CRC_err
R/W
EOT MNI
R R/W
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The MISC register is actually a command + status to control the desired FIFO action and to show the status of the desired FIFO. Every bits meaning and usage are listed as follows: Bit No. 7 6 5 4 3 2 1 0 Function Len0 Ready Set CMD Sel_pipe1 Sel_pipe0 Clear Tx Request Read/Write R/W R R/W R/W R/W R/W R/W R/W 01000110B Register Address
MISC (46H) Registers Table Function Name Request Read/Write R/W Description After setting the other desired status, FIFO can be requested by setting this bit high active. After work has been done, this bit must be set low. Represents the direction and transition end of the MCU accesses. When being set as logic 1, the MCU wants to write data to FIFO. After work has been done, this bit must be set to logic 0 before terminating the request to represent a transition end. For reading action, this bit must be set to logic 0 to indicate that the MCU wants to read and must be set to logic 1 after work is done. Represents MCU clear requested FIFO, even if FIFO is not ready. Determines which FIFO is desired, 00 for FIFO0, 01 for FIFO1, 10 for FIFO 2 and 11 for FIFO3 Shows that the data in FIFO is setup as command. This bit will be cleared by firmware. So, even if the MCU is busy, nothing is missed by the SETUP command from the host. Indicates that the desired FIFO is ready to work. Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after the next valid SETUP token is received. MISC Function Table The HT82M9BEE/HT82M9BAE have two 88 bidirectional FIFO for the three endpoints (control and Interrupt). User can easily read/write the FIFO data by accessing the corresponding FIFO pointer register (FIFO0, FIFO1, FIFO2, FIFO3). The following are two examples for reading and writing the FIFO data: HT82M9BEE/HT82M9BAE FIFO is read by packet. To read from FIFO, the following should be followed:
* Select one set of FIFO, set in the read mode (MISC
Tx
R/W
Clear Sel_pipe1 Sel_pipe0 Set CMD Ready Len0
R/W R/W R/W R R/W
The HT82M9BEE/HT82M9BAE allows a maximum of 8 bytes of data in each packet. The HT82M9BEE/HT82M9BAE FIFO is written by packet. To write to FIFO, the following should be followed:
* Select a set of FIFO, set in the write mode (MISC TX
bit = 1), and set the REQ bit to 1
* Check the ready bit until the status = 1 * Write through the FIFO pointer register and take down
TX bit = 0), and set the REQ bit to 1.
* Check the ready bit until the status = 1 * Read through the FIFO pointer register, and record
the data number that has been written
* Repeat steps 2 and 3 until writing is complete or the
the data number that has been read.
* Repeat steps 2 and 3 until the ready bit becomes 0
ready bit becomes 0 which indicates that the FIFO no longer allows any data writing. * Set MISC TX bit = 0
* Clear the REQ bit to 0. Complete writing.
which indicates the end of the FIFO data reading.
* Set MISC TX bit = 1 * Clear the REQ bit to 0. Complete reading.
User reads the data through the FIFO pointer register, user has to record the number of bytes to be read. Rev. 1.20 22
User writes the data through the FIFO pointer register, user has to record the number of bytes that have been written. The HT82M9BEE/HT82M9BAE allows a maximum of 8 bytes of data in each packet.
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There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform reading, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing and clearing. Actions Read FIFO0 sequence Write FIFO1 sequence Check whether FIFO0 can be read or not Check whether FIFO1 can be written to or not Write 0-sized packet sequence to FIFO 0 MISC Setting Flow and Status 00H(R)01H(R)delay of 2ms, check 41H(R)read* from FIFO0 register and check if not ready (01H)(R)03H(R)02H 0AH(R)0BH(R)delay of 2ms, check 4BH(R)write* to FIFO1 register and check if not ready (0BH)(R)09H(R)08H 00H(R)01H(R)delay of 2ms, check 41H (if ready) or 01H (if not ready) (R)00H 0AH(R)0BH(R)delay of 2ms, check 4BH (if ready) or 0BH (if not ready) (R)0AH 02H(R)03H(R)delay of 2ms, check 43H(R)01H(R)00H
Note: *: There are 2ms gap existing between 2 reading actions or between 2 writing actions Register Name FIFO0 FIFO1 FIFO2 FIFO3 R/W R/W R/W R/W R/W Register Address 01001000B 01001001B 01001010B 01001011B Bit7~Bit0 Data7~Data0 Data7~Data0 Data7~Data0 Data7~Data0
FIFO Register Address Table USB Active Pipe Timing The USB active pipe accessed by the host cannot be used by the MCU simultaneously. When the host finishes its work, the signal, a USB_INT will be produced to tell the MCU that the pipe can be used and the acted pipe No. will be shown in the signal, ACT_PIPE as well. The timing is illustrated in the figure below.
A C T _ P IP E
U S B _ IN T
L a s t A c te d P ip e
USB Active Pipe Timing
Suspend Wake-Up and Remote Wake-Up If there is no signal on the USB bus for over 3ms, the HT82M9BEE/HT82M9BAE will go into a suspend mode. The Suspend line (bit 0 of the USC) will be set to 1 and a USB interrupt is triggered to indicate that the HT82M9BEE/HT82M9BAE should jump to the suspend state to meet the 500mA USB suspend current spec. In order to meet the 500mA suspend current, the programmer should disable the USB clock by clearing the USBCKEN (bit3 of the SCC) to 0. The suspend current is 400mA. When the resume signal is sent out by the host, the HT82M9BEE/HT82M9BAE will wake-up the MCU by USB interrupt and the Resume line (bit 3 of the USC) is set. In order to make the HT82M9BEE/HT82M9BAE function properly, the programmer must set the USBCKEN (bit 3 of the SCC) to 1 and clear the SUSP2 (bit4 of the SCC). Since the Resume signal will be
cleared before the Idle signal is sent out by the host and the Suspend line (bit 0 of the USC) is going to 0. So when the MCU is detecting the Suspend line (bit0 of the USC), the Resume line should be remembered and taken into consideration. After finishing the resume signal, the suspend line will go inactive and a USB interrupt is triggered. The following is the timing diagram:
SUSPEND U S B R e s u m e S ig n a l
U S B _ IN T
The device with remote wake-up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of USC). Once the USB Host receive the wake-up signal
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from the HT82M9BEE/HT82M9BAE, it will send a Resume signal to the device. The timing is as follows:
SUSPEND M in . 1 U S B C L K RMW K
M in .2 .5 m s
is defined as PS2 interface, pin USBD- is now defined as PS2 Data pin and USBD+ is now defined as PS2 Clk pin. The user can easily read or write to the PS2 Data or PS2 Clk pin by accessing the corresponding bit PS2DAI (bit 4 of the USC), PS2CKI (bit 5 of the USC), PS2DAO (bit 6 of the USC) and S2CKO (bit 7 of the USC) respectively. The user should make sure that in order to read the data properly, the corresponding output bit must be set to 1. For example, if user wants to read the PS2 Data by reading PS2DAI, the PS2DAO should be set to 1. Otherwise it always read a 0. If SPS2=0, and SUSB=1, the HT82M9BEE/ HT82M9BAE is defined as a USB interface. Both the USBD- and USBD+ are driven by the USB SIE of the HT82M9BEE/HT82M9BAE. User only writes or reads the USB data through the corresponding FIFO. Both SPS2 and SUSB default is 0.
U S B R e s u m e S ig n a l
U S B _ IN T
To Configure the HT82M9BEE/HT82M9BAE as PS2 Device The HT82M9BEE/HT82M9BAE can be defined as a USB interface or a PS2 interface by configuring the SPS2 (bit 4 of the USR) and SUSB (bit 5 of the USR). If SPS2=1, and SUSB=0, the HT82M9BEE/HT82M9BAE
I/O Port Special Registers Definition
* Port-A (12H) - PA
Bit No. 0~3 4~6 7
Label PA0~PA3 PA4~PA6 PA7
Read/Write R/W R/W R/W
Option 3/4 3/4 3/4
Functions I/O (R/W) has pull-low and pull-high option. Has falling edge wake-up option. I/O (R/W) has pull-high option. Has falling edge wake-up option. I/O (R/W) has pull-high option. Has falling edge wake-up option, pin-shared with timer input pin. PA (12H) Register
* Port-A Control (13H) - PAC
This port configure the input or output mode of Port-A
* Port-B Control (14H) - PB
Bit No. 0 1 2 3 4 5 6 7
Label PB0 PB1 PB2 PB3 PB4/SDA PB5 PB6 PB7/SCL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Option 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Functions I/O (R/W), has pull-high option I/O (R/W), has pull-high option I/O (R/W), has pull-low and pull-high option I/O (R/W), has pull-low and pull-high option I/O (R/W), has pull-high option, can wake-up I/O (R/W), has pull-high option I/O (R/W), has pull-high option I/O (R/W), has pull-high option, can wake-up PB (14H) Register
* Port-B Control (15H) - PBC
This port configures the input or output mode of Port-B for I/O mode
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HT82M9BEE/HT82M9BAE
* Port-C Control (16H) - PC
Bit No. 0~3 4~7
Label PC0~PC3 PC4~PC7
Read/Write R/W R/W
Option 3/4 3/4
Functions I/O (R/W), has pull-high option Reserved PC (16H) Register
* Port-C Control (17H) - PCC
This port configures the input or output mode of Port-C USB/PS2 Status and Control Register - USC Bit No. 0 1 2 3 4 5 6 7 Label PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Read/Write R W R/W R R R W W Option SUSPEND Functions USB suspend mode status bit. When 1, indicates that the USB system entry is in suspend mode.
RMOT_WK USB remote wake-up signal. The default value is 0. URST_FLAG USB bus reset event flag. The default value is 0. RESUME_O PS2_DAI PS2_CKI PS2_DAO PS2_CKO When RESUME_OUT EVENT, RESUME_O is set to 1. The default value is 0. USBD-/DATA input USBD+/CLK input Output for driving USBD-/DATA pin, when working under 3D PS2 mouse function. The default value is 1. Output for driving USBD-/DATA pin, when working under 3D PS2 mouse function. The default value is 1.
USC (0X1A) Register Endpoint Interrupt Status Register - USR The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select the serial bus (PS2 or USB). The endpoint request flags (EP0IF, EP1IF, EP2IF and EP3IF) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to 1 and a USB interrupt will occur (If a USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint request flag has to be cleared to 0. Bit No. 0 1 2 3 4 5 6 7 Label PEC0 PEC1 PEC2 PEC3 PEC4 PEC5 PEC6 PEC7 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Option EP0IF EP1IF EP2IF EP3IF SELPS2 SELUSB 3/4 USB_flag Functions When set to 1, indicates an endpoint 0 interrupt event. Must wait for the MCU to process the interrupt event and clear this bit by firmware. This bit must be 0, then the next interrupt event will be processed. The default value is 0. When set to 1, indicates that the chip is working under PS2 mode. The default value is 0. When set to 1, indicates that the chip is working under USB mode. The default value is 0. Reserved bit, set to 0 This flag is used to show that the MCU is in USB mode (Bit=1). This bit is R/W by FW and will be cleared to zero after power-on reset. The default value is 0.
USR (0X1B) Register
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Clock Control Register - SCC There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB clock control bit (USBCKEN), second suspend mode control bit (SUSPEND2) and system clock selection (SCLKSEL). Bit No. 0~2 3 Label PF0~PF2 PF3 Read/Write R/W R/W Option 3/4 USBCKEN Functions Reserved, must set to 0. USB clock control bit. When set to 1, indicates a USBCK ON, else USBCK OFF. The default value is 0.
4
PF4
R/W
This bit is used to reduce power consumption in the suspend mode. In the normal mode this bit must be cleared to zero(DeSUSPEND2 fault=0). In the HALT mode this bit should be set high to reduce power consumption and LVR with no function. In the USB mode this bit cannot be set high. 3/4 Reserved, must set to 0. System clock 6MHz or 12MHz option, when working on external oscillator mode. The default value is 0. 0: Operating at external 12MHz mode 1: Operating at external 6MHz mode The default value is 0. This flag is used to show that the MCU is in PS2 mode (Bit=1). This bit is R/W by FW and will be cleared to zero after power-on reset. The default value is 0.
5
PF5
R/W
6
PF6
R/W
SCLKSEL
7
PF7
R/W
PS2_flag
SCC (0X1C) Register Table High Byte Pointer for Current Table Read - TBHP Bit No. 4~0 Label PGC4~PGC0 Read/Write R/W Option 3/4 Functions Store current table read bit12~bit8 data
TBHP (0X1F) Register Options No. 1 2 3 4 5 6 7 8 9 10 11 WDT clock source: RC (system/4) (default: T1) WDT clock source: enable/disable for normal mode (default: disable) PA0~PA7 ,PB4/SDA, PB7/SCL wake-up by bit (PA2, PA3 both wake-up by falling or rising edge) (default: non wake-up) PA0~PA7 pull-high by bit (default: pull-high) PB pull-high by bit (default: pull-high) PC pull-high by nibble (default: pull-high) LVR enable/disable (default: enable) PA0~PA3, PB2, PB3 pull-low by bit (default: non pull-low 30kW) CLR WDT, 1 or 2 instructions TBHP enable/disable (default: disable) PA output mode (CMOS/NMOS/PMOS) by bit (default: CMOS) Option
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HT82M9BEE/HT82M9BAE
Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications
VDD USBUSB+ VSS 0 .1 m F
5W
*
10mF
33W
*
0 .1 m F 1 M W *** 22pF
*
VDD
PA0~PA7
100kW
P B 0 ~ P B 3 , P B 4 /S D A P B 5 ~ P B 6 , P B 7 /S C L
5W
*
10kW 0 .1 m F
** 22pF ** 0 .1 m F
X1
OSC1
PC0~PC3
V33O
1 .5 k W
0 .1 m F
OSC2
47pF*
*
RES
U S B D -/D A T A 47pF*
33W
* *
*
VSS U S B D + /C L K
*
47pF 33W
H T 8 2 M 9 B E E /H T 8 2 M 9 B A E
*
47pF
Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES high. X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only. Components with *** are used for 12MHz application.
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC[M](5) Read ROM code (locate by TBLPand TBHP) to data memory and TBLH TABRDC [m](6) Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF 2(1) 2(1) 2(1) None None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. : ROM code TBHP option is enabled : ROM code TBHP option is disabled
(5) (6)
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Rev. 1.20
30
August 13, 2007
HT82M9BEE/HT82M9BAE
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
31
August 13, 2007
HT82M9BEE/HT82M9BAE
CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Rev. 1.20
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HT82M9BEE/HT82M9BAE
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
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HT82M9BEE/HT82M9BAE
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
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HT82M9BEE/HT82M9BAE
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 Rev. 1.20 PDF 3/4 OV 3/4 37 Z 3/4 AC 3/4 C O August 13, 2007
HT82M9BEE/HT82M9BAE
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
38
August 13, 2007
HT82M9BEE/HT82M9BAE
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
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HT82M9BEE/HT82M9BAE
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (locate by TBLP and TBHP) to TBLH and data memory (ROM code TBHP is enabled) The low byte of ROM code addressed by the table pointers (TBLPand TBHP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory (ROM code TBHP is disabled) The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
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August 13, 2007
HT82M9BEE/HT82M9BAE
TABRDL [m] Description Operation Affected flag(s) TO 3/4 XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.20
42
August 13, 2007
HT82M9BEE/HT82M9BAE
Package Information
24-pin SOP (300mil) Outline Dimensions
24 A
13 B
1
12
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 590 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 614 104 3/4 3/4 38 12 10
Rev. 1.20
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August 13, 2007
HT82M9BEE/HT82M9BAE
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
Rev. 1.20
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HT82M9BEE/HT82M9BAE
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 24W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 24.8+0.3 -0.2 30.20.2
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 24.8+0.3 -0.2 30.20.2
Rev. 1.20
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August 13, 2007
HT82M9BEE/HT82M9BAE
Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P
K0 A0
SOP 24W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 240.3 120.1 1.750.1 11.50.1 1.55+0.1 1.5+0.25 40.1 20.1 10.90.1 15.90.1 3.10.1 0.350.05 21.3
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 240.3 120.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 40.1 20.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
Rev. 1.20
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August 13, 2007
HT82M9BEE/HT82M9BAE
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
47
August 13, 2007

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